Class: OrigenDocHelpersDev::DUT::SubModule

Inherits:
Object
  • Object
show all
Includes:
Origen::Model
Defined in:
lib/origen_doc_helpers_dev/dut.rb

Overview

Example to test a real life use case with backslashes in the descriptions which led to rendering issues

Instance Method Summary collapse

Constructor Details

#initialize ⇒ SubModule

Returns a new instance of SubModule.



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# File 'lib/origen_doc_helpers_dev/dut.rb', line 10

def initialize
  reg :debug_18, 0xf44, 32, bit_order: 'lsb0', ip_base_address: 0x1080000, description: '' do
    bit 31..0, :placeholder, reset: 0b0, access: :rw
  end
  reg :debug_19, 0xF48, size: 32, bit_order: :lsb0 do |reg|
    # When this bit is set, the controller\'s state machines and queues will be reset. Software then needs to clear this bit to allow the controller to function. This bit can only be set when DDR\_SDRAM\_CFG\[MEM\_EN\] is cleared.
    #
    # 0 | Memory controller is not reset.
    # 1 | Memory controller is reset.
    reg.bit 31, :mcsr, reset: 0b0, access: :rw
    # These are spare configuration bits that can be written or read. However, they are not currently used by the controller.
    reg.bit 30, :spare_cnfg3, reset: 0b0, access: :rw
    # This bit can be set to force the controller to start write leveling. This bit will be cleared by hardware after write leveling is complete.
    reg.bit 29, :frc_wrlvl, reset: 0b0, access: :rw
    # If this bit is cleared and automatic CAS to Preamble is used, then the DDR controller will calculate the write leveling start values for DQS\[1:8\] based on the CAS to Preamble results and the start value for DQS\[0\]. If this bit is set, then the automatic calculation of the start value is disabled.
    reg.bit 28, :wrc_dis, reset: 0b0, access: :rw
    # These are spare configuration bits that can be written or read. However, they are not currently used by the controller.
    reg.bit 27, :spare_cnfg2, reset: 0b0, access: :rw
    # If this bit is set, then the chip select specified by CSWL will be used during write leveling.
    reg.bit 26, :cswlo, reset: 0b0, access: :rw
    # This field represents the chip select that will be used during write leveling if CSWLO is set.
    reg.bit 25..24, :cswl, reset: 0b0, access: :rw
    # This can be set to use an internally generated VRef.
    #
    # 0 | Default.
    # 1 | Use internal VRef.
    reg.bit 23, :int_ref_sel, reset: 0b0, access: :rw
    reg.bit 22, :ign_cas_full, reset: 0b0, access: :rw
    # This bit can be set to override the perfmon enable to the controller.
    #
    # 0 | Use ipm_plus_perfmon_en.
    # 1 | Ignore ipm_plus_perfmon_en and collect perfmon events.
    reg.bit 21, :perf_en_ovrd, reset: 0b0, access: :rw
    # If this bit is set, then the bit deskew results will not be averaged across the enabled ranks. Instead, the address determined by DDR\_INIT\_ADDR will be used for bit deskew.
    reg.bit 20, :bdad, reset: 0b0, access: :rw
    # This field specifies how many taps will be incremented for each sample during RX bit deskew training. Note that this can be used to improve simulation times when validating the DDR controller RX deskew training.
    #
    # 000 | Increment 1 tap at a time
    # 001 | Increment 2 taps at a time
    # 010 | Increment 4 taps at a time
    # 011 | Increment 6 taps at a time
    # 100 | Increment 8 taps at a time
    # 101 | Increment 10 taps at a time
    # 110 | Increment 12 taps at a time
    # 111 | Increment 14 taps at a time
    reg.bit 19..17, :rx_skip_tap, reset: 0b0, access: :rw
    # If this bit is set, then the MCK gating during self refresh will be disabled.
    reg.bit 16, :mck_dis, reset: 0b0, access: :rw
    # This is the value sent to the IOs for the p\_gnd\_curr\_adj\[0:1\] and n\_gnd\_curr\_adj\[0:1\]
    reg.bit 15..12, :curr_adj, reset: 0b0, access: :rw
    # This is the enable for the TPA pin.
    reg.bit 11, :en_tpa, reset: 0b0, access: :rw
    # This 4-bit value represents the 4-bit MUX select to the TPA pin for.
    reg.bit 10..6, :tpa_mux_sel, reset: 0b0, access: :rw
    # This bit can be set to override the counter free-list group. It can be used to force a certain group only to be enabled.
    reg.bit 5, :cntr_ovrd, reset: 0b0, access: :rw
    # This is the value that will be overridden to the counter logic if CNTR\_OVRD is set. Note that values of 3\'b110 and 3\'b111 are illegal, and the will prevent the controller from finding an available counter to use.
    reg.bit 4..2, :cntr_ovrd_val, reset: 0b0, access: :rw
    # This bit can be set to force the transmit bit deskew to be enabled, regardless of the value of SLOW\_EN.
    reg.bit 1, :tx_bd_en, reset: 0b0, access: :rw
    reg.bit 0, :spare_cnfg, reset: 0b1, access: :rw
  end
  reg :debug_20, 0xf4c, 32, bit_order: 'lsb0', ip_base_address: 0x1080000, description: '' do
    bit 31..0, :placeholder, reset: 0b0, access: :rw
  end
  reg :debug_21, 0xf50, 32, bit_order: 'lsb0', ip_base_address: 0x1080000, description: '' do
    bit 31..0, :placeholder, reset: 0b0, access: :rw
  end
  reg :debug_22, 0xf54, 32, bit_order: 'lsb0', ip_base_address: 0x1080000, description: '' do
    bit 31..0, :placeholder, reset: 0b0, access: :rw
  end
  reg :msb0_debug, 0xf58, 32, bit_order: 'msb0', ip_base_address: 0x1080000, description: '' do
    # placeholder field description
    bit 31..1, :placeholder, reset: 0b0, access: :rw
    # single bit
    bit 0,     :single_bit, reset: 1, access: :rw
  end
  reg :lsb0_non_byte_aligned, 0xf5c, 9, bit_order: 'lsb0', ip_base_address: 0x1080000, description: '' do
    bit 8..0, :placeholder, reset: 0b0, access: :rw
  end
  reg :msb0_non_byte_aligned, 0xf60, 9, bit_order: :msb0, ip_base_address: 0x1080000, description: '' do
    # placeholder field description
    bit 8..0, :placeholder, reset: 0b0, access: :rw
  end
  reg :lsb0_tiny, 0xf64, 3, bit_order: :lsb0, ip_base_address: 0x1080000, description: '' do
    bit 2..0, :placeholder, reset: 0b0, access: :rw
  end
  reg :msb0_tiny, 0xf68, 3, bit_order: :msb0, ip_base_address: 0x1080000, description: '' do
    # placeholder field description
    bit 2..0, :placeholder, reset: 0b0, access: :rw
  end
end